The present invention relates to providing scalable routing and addressing for transactions in a transactions infrastructure.
In many computer environments, a fast and flexible transactions infrastructure can be desirable to provide connectivity to devices capable of high levels of data throughput.
For example, in the fields of data transfer between devices in a computing environment, PCI Express (PCI-E) can be used to provide connectivity between a host and one or more client devices or endpoints. PCI Express is becoming a de-facto I/O interconnect for servers and desktop computers. PCI Express allows physical system decoupling (CPU<->I/O) through high-speed serial I/O. The PCI Express Base Specification 1.0 sets out behavior requirements of devices using the PCI Express interconnect standard. According to the Specification, PCI Express is a host to endpoint protocol where each endpoint connects to a host and is accessible by the host. PCI Express imposes a stringent tree structure relationship between I/O Devices and a Root Complex.
The present invention seeks to facilitate the routing and addressing of transaction packets in a transactions infrastructure in a fast, flexible, efficient and scalable manner.